Experience with a retargetable compiler for a commercial network processor

Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '02

Volumn , Issue , 2002, Pages 178-187

  Kim, Jinhwan ^a   Jung, Sungjoon ^a   Paek, Yunheung ^a   Uh, Gang Ryung ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Boise State University   (United States)

Author keywords

Compiler; Network processor; Non orthogonal architecture

Indexed keywords

ARCHITECTURAL FEATURES; CODE GENERATION; COMMERCIAL NETWORKS; COMPILER; COMPILER TECHNIQUES; INTER-PROCEDURAL; INTERNET SERVICES; NETWORK PROCESSOR; NEW HIGH; REGISTER ALLOCATION; RETARGETABLE COMPILERS; VIRTUAL DATA;

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; INTERNET; NANOTECHNOLOGY; SYNTHESIS (CHEMICAL);

PROGRAM COMPILERS;

EID: 33847173637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581658     Document Type: Conference Paper

References (14)

1. see paion web site : http://www.paion.com.
2. A. Appel, J. Davidson, N. Ramsey. The Zephyr Compiler Infrastructure. Technical Report at http://www.cs.virgina.edu/zephyr, University of Virginia, 1998.
3. M. Benitez, J. Davidson. Target-specific Global Code Improvement: Principles and Applications. Technical Report CS-94-142, University of Virginia, 1994.
4. Keith D. Cooper, Mary W. Hall, Linda Torczon. Unexpected side effects of inline substitution: a case study. ACM Letters on Programming Languages and Systems (LOPLAS), 1(1):22-32, 1992. (Pubitemid 23614063)
5. EZCHIP Technologies. Network Processor Designs for Next-Generation Networking Equipment.
6. Sungjoon Jung, Yunheung Paek. The very portable optimizer for digital signal processors. In Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems, pages 84-92. ACM Press, 2001.
7. R. Leupers., editor. Code Optimization Techniques for Embedded Processors. Kluwer Academic Publishers, 2000.
8. P. Marwedel, G. Goossens, editors. Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995.
9. Xiaoning Nie, L. Gazsi, F. Engel, G. Fettweis. A new network processor architecture for high-speed communications. In Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on, pages 548-557. IEEE Press, 1999.
10. P. Paulin, F. Karim, P. Bromley. Network processors: a perspective on market requirements, processor architectures and embedded s/w tools. In Proceedings of the DATE 2001 on Design, automation and test in Europe, pages 420-429. IEEE Press, 2001.
11. N. Ramsey, J. Davidson. Machine Descriptions to Build Tools for Embedded Systems. In Workshop on Languages, Compilers and Tools for Embedded Systems, 1998.
12. P. A. Steenkiste, J. L. Hennessy. A Simple Interprocedural Register Allocation Algorithm and its Effectiveness for LISP. Transactions on Programming Languages and Systems, pages 1-30, January 1989.
13. A. Sudarsanam. Code Optimization Libraries For Retargetable Compilation For Embedded Digital Signal Processors. PhD thesis, Princeton University Department of EE, May 15, 1998.
14. Jens Wagner, Rainer Leupers. C compiler design for an industrial network processor. In Proceedings of the ACM SIGPLAN workshop on Languages, compilers and tools for embedded systems, pages 155-164. ACM Press, 2001.