The noise and linearity optimization for a 1.9-GHz CMOS low noise amplifier

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Volumn , Issue , 2002, Pages 253-257

  Guo, Wei ^a   Huang, Daquan ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

CMOS LNA; IP3; Linearity; NF; Noise; RFIC

Indexed keywords

ANALOG CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; MOSFET DEVICES; RECONFIGURABLE HARDWARE;

CMOS LNA; CMOS LOW NOISE AMPLIFIERS; COMPUTER SIMULATION EXPERIMENT; IMPROVEMENT TECHNIQUE; LINEARITY; NOISE; RADIO FREQUENCY INTEGRATED CIRCUIT (RFICS); RFIC;

LOW NOISE AMPLIFIERS;

EID: 84966415452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.2002.1031580     Document Type: Conference Paper

References (6)

1. D. K. Shaeffer, et al, "1.5-V, 1.5-GHz CMOS Low Noise Amplifier", Solid-State Circuits, IEEE Journal of Volume: 32, May 1997, pp. 745-759.
2. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge Univ. Press, 1998.
3. Piljae Park, et al, "Linearity, Noise Optimization for Two Stage RF CMOS LNA", Proc. Of IEEE, Volume: 2, 2001, pp. 756-758.
4. th IEEE International Conference on, Volume: 3, 2001, pp. 1611-1614.
5. Wei Jin, et al, "Noise Modeling and Characterization for 1.5-V 1.8-GHz SOI Low-Noise Amplifier", IEEE Transaction on Electron Devices, Volume: 48, No. 4, April 2001, pp. 803-809.
6. A. Van der Ziel, Noise in Solid State Devices and Circuits, New York: Wiley, 1986.