A low power carry select adder with reduced area

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 218-221

  Kim, Youngjoon ^a   Kim, Lee Sup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LENGTHS; CARRY SELECT ADDERS; CMOS TECHNOLOGY; DELAY TIME; LOW POWER; POWER SUPPLY; RIPPLE CARRY ADDERS; ZERO FINDING;

CMOS INTEGRATED CIRCUITS;

ADDERS;

EID: 11244328022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922211     Document Type: Conference Paper

References (4)

1. Chang, T. Y and Hsiao, M. J., "Carry-select adder using single ripple-carry adder". Electronics Letters, vol. 34, No. 22, Oct 1998, pages 2101-2103
2. Rabaey, J. M., Digital Integrated Circuits: A Design perspective. New Jersey, Prentice-Hall, 1996
3. N. Weste and K. Eshragian, Principles of CMOS VLSI Designs: A System Perspective, 2nd ed., Addison-Wesley, 1985-1993:
4. Morinaka, H., Makino, H., Nakase, Y. et. al, "A 64 bit Carry Look-ahead CMOS adder using Modified Carry Select". Custom Integrated Circuit Conference, 1995, pages 585-588.