A 64-bit carry look ahead adder using pass transistor BiCMOS gates

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 810-817

  Ueda, Kimio ^b,c,d   Suzuki, Hiroaki ^b   Suda, Kakutaro ^b   Shinohara, Hirofumi ^b   Mashiko, Koichiro ^a,b  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c NAGAOKA UNIVERSITY OF TECHNOLOGY   (Japan)

^d JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; LOGIC GATES;

CARRY LOOK AHEAD ADDER; INTRINSIC DELAY TIME; PASS TRANSISTOR BICMOS GATES;

ADDERS;

EID: 0030173431     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509867     Document Type: Article

References (12)

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