An efficient functional test for the massively-parallel C•RAM logic-enhanced memory architecture

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 475-484

  Sun, X ^a   Cockburn, B F ^a   Elliott, D G ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; PARALLEL ARCHITECTURES; RANDOM ACCESS STORAGE; RECONFIGURABLE HARDWARE;

COMPUTATIONAL RAM; CONVENTIONAL MEMORY; FUNCTIONAL FAULTS; FUNCTIONAL TEST; INTERNAL MEMORY BANDWIDTHS; LINEAR ARRAYS; MASSIVELY PARALLELS; MEMORY ARRAY;

MEMORY ARCHITECTURE;

EID: 84964920881     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250146     Document Type: Conference Paper

References (10)

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