Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 17.3.1-17.3.4

  Yu, Shimeng ^a   Chen, Pai Yu ^a   Cao, Yu ^a   Xia, Lixue ^b   Wang, Yu ^b   Wu, Huaqiang ^b  

^a ARIZONA STATE UNIVERSITY   (United States)

^b TSINGHUA UNIVERSITY   (China)

Author keywords

crossbar array; machine learning; neuromorphic computing; Resistive memory; synaptic device

Indexed keywords

ARTIFICIAL INTELLIGENCE; ECONOMIC AND SOCIAL EFFECTS; ELECTRON DEVICES; LEARNING SYSTEMS; RECONFIGURABLE HARDWARE;

CROSSBAR ARRAYS; DESIGN CONSIDERATIONS; MITIGATION STRATEGY; NEUROMORPHIC COMPUTING; ON-CHIP IMPLEMENTATIONS; PERIPHERAL CIRCUITS; RESISTIVE MEMORY; SYNAPTIC DEVICE;

LEARNING ALGORITHMS;

EID: 84964078185     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409718     Document Type: Conference Paper

References (13)

1. Q. V. Le, et al. "Building high-level features using large scale unsupervised learning," ICML, 2012.
2. P. A. Merolla, et al. "A million spiking-neuron integrated circuit with a scalable communication network and interface," Science, 2014.
3. P.-Y. Chen, et al. "Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip," DATE, 2015.
4. I-T. Wang, et al. "3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation," IEDM, 2014.
5. S. Park, et al. "Neuromorphic speech systems using advanced ReRAM-based synapse," IEDM, 2013.
6. S. H. Jo, et al. "Nanoscale memristor device as synapse in neuromorphic systems," Nano Lett, 2010.
7. M. Prezioso, et al. "Training and operation of an integrated neuromorphic network based on metal-oxide memristors," Nature, 2015.
8. P.-Y. Chen, et al. "Mitigating effects of non-ideal synaptic device characteristics for on-chip learning," ICCAD, 2015.
9. H. Lee, et al. "Efficient sparse coding algorithms," NIPS, 2006.
10. MNIST, http://yann.lecun.com/exdb/mnist/
11. D. Kadetotad, et al. "Parallel architecture with resistive crosspoint array for dictionary learning acceleration," JETCAS, 2015.
12. CACTI, http://www.hpl.hp.com/research/cacti/
13. NVSim, http://nvsim.org/