Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 2015-April, Issue , 2015, Pages 854-859

  Chen, Pai Yu ^a   Kadetotad, Deepak ^a   Xu, Zihan ^a   Mohanty, Abinash ^a   Lin, Binbin ^a   Ye, Jieping ^a   Vrudhula, Sarma ^a   Seo, Jae Sun ^a   Cao, Yu ^a   Yu, Shimeng ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

cross point array; machine learning; neuromorphic computing; resistive memory; synaptic device

Indexed keywords

CHARACTER RECOGNITION; DESIGN; ENERGY EFFICIENCY; ENERGY UTILIZATION; IMAGE ENHANCEMENT; LEARNING SYSTEMS; MACHINE LEARNING;

CROSS-POINT ARRAY; ENERGY EFFICIENCY IMPROVEMENTS; HANDWRITTEN DIGIT RECOGNITION; NEUROMORPHIC COMPUTING; PERIPHERAL CIRCUITRY; RESISTIVE MEMORY; SYNAPTIC DEVICE; TECHNOLOGY AND DESIGNS;

LEARNING ALGORITHMS;

EID: 84945955645     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2015.0620     Document Type: Conference Paper

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