Hardware prefetching in bus-based multiprocessors: Pattern characterization and cost-effective hardware

Proceedings - 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001

Volumn , Issue , 2001, Pages 345-354

  Garzaran M J ^a   Brit, J L ^a   Ibanez P E ^a   Vinals V ^a  

^a UNIVERSITY OF ZARAGOZA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUSES; COST EFFECTIVENESS; HARDWARE; MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; SHAPE MEMORY EFFECT;

DISTRIBUTED SHARED MEMORY; MEMORY ACCESS LATENCY; MEMORY ACCESS PATTERNS; PATTERN CHARACTERIZATIONS; PERFORMANCE MODEL; PREFETCHING TECHNIQUES; RECENT RESEARCHES; RELATIVE PERFORMANCE;

RECONFIGURABLE HARDWARE;

EID: 84963575852     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMPDP.2001.905061     Document Type: Conference Paper

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