A novel via blockage model and its implications

Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000

Volumn , Issue , 2000, Pages 15-17

  Chen, Qiang ^a   Davis, J A ^a   Zarkesh Ha, Payman ^a   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ARCHITECTURE; STOCHASTIC MODELS; STOCHASTIC SYSTEMS;

CHANNEL AVAILABILITY; INTERCONNECT NETWORKS; LENGTH DISTRIBUTIONS; METAL LEVELS; MULTILEVELS; TRANSISTOR CHIPS; VIA BLOCKAGE; WIRING AREA;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84962815242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2000.854267     Document Type: Conference Paper

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