A hybrid radix-4/radix-8 low power signed multiplier architecture

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 8, 1997, Pages 656-659

  Cherkauer, Brian S ^a   Friedman, Eby G ^b  

^a INTEL CORPORATION   (United States)

^b University of Rochester   (United States)

Author keywords

Low power; Multiplier; Radix

Indexed keywords

DELAY CIRCUITS; ELECTRIC LOSSES; EQUALIZERS;

RADIX PARTIAL PRODUCTS;

MULTIPLYING CIRCUITS;

EID: 0031209569     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.618039     Document Type: Article

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