VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 435-440

  Seth, K ^a   Srinivasan, S ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDPASS FILTERS; COMPUTER AIDED DESIGN; DESIGN; DISCRETE WAVELET TRANSFORMS; FILTER BANKS; RECONFIGURABLE HARDWARE; SCHEDULING ALGORITHMS;

2-D DISCRETE WAVELET TRANSFORMS; COMMON SUBEXPRESSION SHARING; INVERSE DISCRETE WAVELET TRANSFORMS; MEMORY REQUIREMENTS; PERFORMANCE MEASURE; RECONSTRUCTED IMAGE; SYMMETRIC EXTENSION; VLSI IMPLEMENTATION;

WAVELET TRANSFORMS;

EID: 84962230853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994959     Document Type: Conference Paper

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