Effects of beam incident angle control on NMOS source/drain extension applications

Proceedings of the International Conference on Ion Implantation Technology

Volumn 22-27-September-2002, Issue , 2002, Pages 64-68

  Jeong, Ukyo ^a   Mehta, Sandeep ^a   Campbell, Chris ^a   Lindberg, Robert ^a   Zhao, Zhiyong ^b   Cusson, Brian ^b   Buller, James ^b  

^a VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

batch implanter; beam divergence; beam parallelism; component; ion implant; dose matching; SDE doping; single wafer implanter; source drain

Indexed keywords

CMOS INTEGRATED CIRCUITS; ION BEAMS; IONS;

BATCH IMPLANTER; BEAM DIVERGENCE; BEAM PARALLELISM; DOSE MATCHING; ION IMPLANT; SINGLE WAFER; SOURCE/DRAIN;

ION IMPLANTATION;

EID: 84961382383     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IIT.2002.1257939     Document Type: Conference Paper

References (6)

1. T. Yamashita et al., "Advanced retrogradewell technology for 90-nmnode embedded static random access memory using high-energy parallel beam", April, 2002, Jpn. J. Appl. Phys. Vol. 41
2. S. Walther et al., "Dopant channeling as a function of implant angle for low energy applications", IIT 1998
3. U. Jeong et al. ""Devices dictate control of implant-beam incident angle", Solid State Technology, Oct. 2001
4. G. Angel et al., "A novel beam line for sub-keV implants with reduced energy contamination", IIT 1998
5. C. Campbell et al., "Beam angle control on the VIISta 80 ion implanter", IIT 2002
6. T. Ghani et al., "Scaling challenges and device design requirements for high performance sub-50nm gate length planar CMOS transistors", 2000, VLSI symposium