Intermetallic formation in the Sn-Ag solder joints between Au stud bumps and Cu pads and its effect on the chip shear strength

Advances in Electronic Materials and Packaging 2001

Volumn , Issue , 2001, Pages 155-162

  Shin, Mu Seob ^a   Kim, Young Ho ^a   Do, Won Chul ^b   Ha, Sun Ho ^b   Min, Byung Yul ^b  

^a Hanyang University   (South Korea)

^b Amkor Technology Korea Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; CHIP SCALE PACKAGES; ELECTRONICS PACKAGING; GOLD; INTERMETALLICS; LEAD-FREE SOLDERS; MODIFIED ATMOSPHERE PACKAGING; PRINTED CIRCUIT BOARDS; PRINTED CIRCUITS; SHEAR FLOW; SILVER; SOLDERING ALLOYS; STUDS (FASTENERS); STUDS (STRUCTURAL MEMBERS);

CONTINUOUS LAYERS; CU-SN INTERMETALLICS; INTERMETALLIC FORMATION; INTERMETALLIC LAYER; MULTIPLE REFLOWS; PRINTED CIRCUIT BOARDS (PCB); STENCIL PRINTING; WIRE BONDING TECHNOLOGY;

TIN;

EID: 84960356461     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMAP.2001.983976     Document Type: Conference Paper

References (9)

1. Shinichi Terashima, Tomohiro Uno, Eiji Hashino and Kohei Tatsumi, "Improvement in Thermal Reliability of A Flip Chip Interconnection System Joined by Pb-Free Solder and Au bumps", Materials Transactions, Vol. 42, No. 5 (2001), pp. 803-808.
2. J. H. Lau, Flip Chip Technologies, McGraw-Hill (New York, 1996), pp. 1-82.
3. W. Reinert, T. Harder, "Performance of the stud bump bonding (SBB) Process in Comparison to Solder Flip Chip Technology", Proc. IEEE 2000, pp. 136-140.
4. Frederic Ferrando, Jean-Francois Zeberli, Philippe Clot, and Jean-Marc Chenuz, "Industrial approach of a Flip Chip method using the stud bumps with a non-conductive paste", Proc. IEEE 2000, pp.205-211.
5. CL Wong and James How, "Low Cost Flip Chip Bumping Technologies", 1997 IEEE/CPMT Electronic Packaging Technology Conference, pp. 244-250.
6. Toru Ishida, "Advanced Substrate and Packaging Technology", Proc. 1998 IEMT/IMC, pp. 18-24.
7. Ho-Cheol Jang, Chul-Won Jee, Young-Ho Kim, In-Baek Park, Sung-Min Seo, and Byung-Yul Min, "A study on the reliability of stencil printed solder bumps", 2000 IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp.288-293.
8. Satoru Zama, Daniel F. Baldwin, and Toshiya Hikami, "Flip Chip Interconnect System Using Wire Stud Bumps and Lead Free Solder", 2000 IEEE/Electronic Components and Technology Conference, pp. 1111-1117.
9. B. F. Dyson: J. Appl. Phys. 37 (1966), pp.2375-2377.