Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Volumn 2015-October, Issue , 2015, Pages 25-30

  Gautschi, Michael ^a   Traber, Andreas ^a   Pullini, Antonio ^a   Benini, Luca ^a   Scandale, Michele ^b   Di Federico, Alessandro ^b   Beretta, Michele ^b   Agosta, Giovanni ^b  

^a ETH ZURICH   (Switzerland)

^b POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CLOSED LOOP CONTROL SYSTEMS; CLUSTER ANALYSIS; CLUSTER COMPUTING; CODES (SYMBOLS); ENERGY EFFICIENCY; INTEGRATED CIRCUIT TESTING; MEMORY ARCHITECTURE; NUMERICAL METHODS; PARALLEL PROCESSING SYSTEMS; PIPELINES; PROGRAM COMPILERS;

COMPUTATION INTENSIVES; CRITICAL PATH LENGTHS; INSTRUCTION CACHES; INSTRUCTION SET EXTENSION; MICRO ARCHITECTURES; MULTI-CORE CLUSTER; PARALLEL APPLICATION; PARALLEL EXECUTIONS;

COMPUTER ARCHITECTURE;

EID: 84960084962     PISSN: 23248432     EISSN: 23248440     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI-SoC.2015.7314386     Document Type: Conference Paper

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