Evaluating the XMT parallel programming model

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2026, Issue , 2001, Pages 95-108

  Naishlos, Dorit ^a   Nuzman, Joseph ^b,c   Tseng, Chau Wen ^a,c   Vishkin, Uzi ^b,c,d  

^a Institute of Advanced Computer Science   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

^c UNIVERSITY OF MARYLAND   (United States)

^d TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MULTITASKING; PARALLEL PROGRAMMING;

EXECUTION MODEL; LOW OVERHEAD; MULTI-THREADING; ON CHIP MEMORY; ON-CHIP PARALLELISM; PARALLEL PROGRAMMING MODEL; PROGRAMMING MODELS; TASK ASSIGNMENT;

PROGRAM COMPILERS;

EID: 84959055201     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45401-2_8     Document Type: Conference Paper

References (17)

1. G.E. Blelloch, et al, "A Comparison of Sorting Algorithms for the Connection Machine CM-2," Symposium on Parallel Algorithms and Architectures, pp. 3-16, July 1991.
2. D. Burger and T.M. Austin, "The SimpleScalar Tool Set, Version 2.0," Tech. Report CS-1342, University of Wisconsin-Madison, June 1997.
3. E. Berkovich, J. Nuzman, M. Franklin, B. Jacob, and U. Vishkin, "XMT-M: A scalable decentralized processor," UMIACS TR 99-55, September 1999.
4. B.L. Chamberlain, S.J. Deitz, and L. Snyder, "A Comparative Study of the NAS MG Benchmark across Parallel Languages and Architectures," Proc. of Supercomputing (SC), 2000.
5. F. Cappello and D. Etiemble, "MPI versus MPI+OpenMP on the IBM SP for the NAS Benchmarks," Proc. of Supercomputing (SC), 2000.
6. S. Dascal and U. Vishkin, "Experiments with List Ranking on Explicit Multi-Threaded (XMT) Instruction Parallelism," Proc. 3rd Workshop on Algorithms Engineering (WAE-99), July 1999, London, U.K.
7. M. Frigo, C. Leiserson, and K. Randall, "The Implementation of the Cilk-5 Multi-threaded Language," Proc. of the 1998 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1998.
8. M. Franklin, "The Multiscalar Architecture," Ph.D. thesis. Technical Report TR 1196, Computer Sciences Department, University of Wisconsin-Madison, December 1993.
9. D.S. Henty, "Performance of Hybrid Message-Passing and Shared-Memory Parallelism for Discrete Element Modeling," Proc. of Supercomputing (SC), 2000.
10. L. Hammond, B. Nayfeh, and K. Olukotun, "A Single-Chip Multiprocessor," IEEE Computer, Vol. 30, pp. 79-85, September 1997.
11. D. Naishlos, J. Nuzman, C.-W. Tseng, and U. Vishkin, "Evaluating Multi-threading in the Prototype XMT Environment," In Proc. 4th Workshop on Multi-Threaded Execution, Architecture and Compliation (MTEAC2000), December 2000.
12. H. Shan, J.P. Singh, L. Oliker, and R. Biswas, "A Comparison of Three Programming Models for Adaptive Aplications on the Origin2000," Proc. of Supercomputing (SC), 2000.
13. D. Tullsen, J. Lo, S. Eggers, and H. Levy, "Supporting Fine-Grained Synchronization on a Simultaneous Multi-threading Processor," Proc. of the 5th International Symposium on High Performance Computer Architecture, 1999.
14. U. Vishkin, S. Dascal, E. Berkovich, and J. Nuzman, "Explicit Multi-threaded (XMT) Bridging Models for Instruction Parallelism," Proc. 10th ACM Symposium on Parallel Algorithms and Architectures (SPAA), pp. 140-151, 1998.
15. U. Vishkin, "A No-Busy-Wait Balanced Tree Parallel Algorithmic Paradigm," Proc. 12th ACM Symposium on Parallel Algorithms and Architectures (SPAA), 2000.
16. E. Waingold, M. Tayor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal, "Baring It All to Software: Raw Machines," IEEE Computer, Vol. 30, pp. 86-93, September 1997.
17. R. Wilson et al. "SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers," ACM SIGPLAN Notices, v. 29, n. 12, pp. 31-37, December 1994.