Automatic error correction of large circuits using Boolean decomposition and abstraction

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1703, Issue , 1999, Pages 157-172

  Hoffmann, Dirk W ^a   Kropf, Thomas ^a  

^a UNIVERSITY OF TÜBINGEN   (Germany)

Author keywords

Automatic error correction; Design error diagnosis; Equivalence checking; Formal methods

Indexed keywords

ABSTRACTING; COMBINATORIAL CIRCUITS; DESIGN; ERROR CORRECTION; ERRORS; FORMAL METHODS; FORMAL SPECIFICATION; HARDWARE; RECONFIGURABLE HARDWARE; SPECIFICATIONS;

BENCHMARK CIRCUIT; BOOLEAN DECOMPOSITION; DESIGN ERRORS; EQUIVALENCE CHECKER; EQUIVALENCE CHECKING; PROPOSITIONAL FORMULAS; STRUCTURAL SIMILARITY; STRUCTURE-BASED;

ELECTRIC RECTIFIERS;

EID: 84958613660     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_13     Document Type: Conference Paper

References (21)

1. M. S. Abadir, J. Ferguson, and T. E. Kirkland. Logic design verification via test generation. IEEE Transactions on CAD, 7(1):138–148, January 1988.
2. D. Brand. The taming of synthesis. In International Workshop on Logic Synthesis, May 1991.
3. D. Brand. Incremental synthesis. In Proceedings of the International Conference on Computer Aided Design, pages 126–129, 1992.
4. D. Brand. Verification of Large Synthesized Designs. In IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 534–537, Santa Clara, California, November 1993. ACM/IEEE, IEEE Computer Society Press.
5. D. Brand, A. Drumm, S. Kundu, and P. Narain. Incremental synthesis. In Proceedings of the International Conference on Computer Aided Design, pages 14–18, 1994.
6. R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. The Kluwer International Series in Engineering and Computer Science. Kluwer Academic Publishers, 1986.
7. F. Brglez and H. Fujiwara. A neutral netlist of 10 combinatorial benchmark circuits and a target translator in FORTRAN. In Int. Symposium on Circuits and Systems, Special Session on ATPG and Fault Simulation, 1985.
8. R. E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677–691, August 1986.
9. R. E. Bryant. Symbolic boolean manipulation with ordered binary decision diagrams. ACM Computing Surveys, 24(3):293–318, September 1992.
10. P. Y. Chung, Y. M. Wang, and I. N. Hajj. Diagnosis and correction of logic design errors in digital circuits. In Proceedings of the 30th Design Automation Conference (DAC), 1993.
11. A. Gupta. Formal Hardware Verification Methods: A Survey. Journal of Formal Methods in System Design, 1:151–238, 1992.
12. D. W. Hoffmann and T. Kropf. AC/3 V1.00 - A Tool for Automatic Error Correction of Combinatorial Circuits. Technical Report 5/99, University of Karlsruhe, 1999. available at http://goethe.ira.uka.de/∼hoff.
13. Alan J. Hu. Formal hardware verification with BDDs: An introduction. In IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing (PACRIM), pages 677–682, October 1997.
14. S. Y. Huang, K. C. Chen, and K. T. Cheng. Error correction based on verification techniques. In Proceedings of the 33rd Design Automation Conference (DAC), 1996.
15. J. C. Madre, O. Coudert, and J. P. Billon. Automating the diagnosis and the rectification of design errors with PRIAM. In Proceedings of ICCAD, pages 30–33, 1989.
16. S. M. Reddy, W. Kunz, and D. K. Pradhan. Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. In ACM/IEEE Design Automation Conference, pages 414–419, 1995.
17. M. Tomita and H. H. Jiang. An algorithm for locating logic design errors. In IEEE International Conference of Computer Aided Design (ICCAD), 1990.
18. M. Tomita, T. Yamamoto, F. Sumikawa, and K. Hirano. Rectification of multiple logic design errors in multiple output circuits. In Proceedings of the 31st Design Automation Conference (DAC), 1994.
19. A. Veneris and I. N. Hajj. Correcting multiple design errors in digital VLSI circuits. In IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, Florida, USA, May 1999.
20. A. Wahba and D. Borrione. A method for automatic design error location and correction in combinational logic circuits. Journal of Electronic Testing: Theory and Applications, 8(2):113–127, April 1996.
21. A. Wahba and D. Borrione. Connection errors location and correction in combinational circuits. In European Design and Test Conference ED& TC-97, Paris, France, March 1997.