Correcting multiple design errors in digital VLSI circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages

  Veneris, Andreas G ^a   Hajj, Ibrahim N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR ANALYSIS; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

BINARY DECISION DIAGRAM; ERROR DIAGNOSIS; MULTIPLE DESIGN ERROR; TEST VECTOR SIMULATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032682017     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)