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Volumn 1478, Issue , 1998, Pages 323-334

General purpose computer architecture based on fully programmable logic

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENERAL PURPOSE COMPUTERS; HARDWARE; MEMORY ARCHITECTURE; MESSAGE PASSING; PLASTIC PARTS; RECONFIGURABLE HARDWARE; STORAGE ALLOCATION (COMPUTER);

EID: 84957363928     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0057634     Document Type: Conference Paper
Times cited : (11)

References (14)
  • 1
    • 11744286823 scopus 로고
    • Synthesis From Pure Behavioral Descriptions
    • Edited by R. Camposano and W. Wolf, Kluwer Academic Publishers,June
    • Y. Nakamura, K. Oguri and A. Nagoya: "Synthesis From Pure Behavioral Descriptions," High-Level VLSI Synthesis, Edited by R. Camposano and W. Wolf, Kluwer Academic Publishers, pp.205-229, June, 1991 http://www.keel.ntt.co.jp/car/parthe/
    • (1991) High-Level VLSI Synthesis , pp. 205-229
    • Nakamura, Y.1    Oguri, K.2    Nagoya, A.3
  • 11
    • 0012051360 scopus 로고
    • Run Time Reconfiguration of FPGAs for Scanning Geomic DataBases
    • P. Athanas and K.L. Pocek (eds.), IEEE Computer Society Press
    • E. Lemoine and D. Merceron: "Run Time Reconfiguration of FPGAs for Scanning Geomic DataBases," in Proc. FCCM95, P. Athanas and K.L. Pocek (eds.), IEEE Computer Society Press, pp. 85-89, 1995
    • (1995) Proc. FCCM95 , pp. 85-89
    • Lemoine, E.1    Merceron, D.2
  • 12


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.