Parallelization in co-compilation for configurable accelerators

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 23-33

  Becker, J ^a   Hartenstein, R ^a   Herz, M ^a   Nageldinger, U ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS;

CO-COMPILATION METHODS; CONFIGURABLE ACCELERATORS; PARALLELIZATION METHODS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032218710     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (51)