Approach to verify a large scale system-on-a-chip using symbolic model checking

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 308-313

  Takayama, Koichiro ^a   Satoh, Taizo ^a   Nakata, Tsuneo ^a   Hirose, Fumiyasu ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ERRORS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; TRANSISTORS; USER INTERFACES; VLSI CIRCUITS;

SYMBOLIC MODEL CHECKING; SYSTEM LEVEL VERIFICATION; SYSTEM ON A CHIP;

COMPUTER SIMULATION;

EID: 0032288884     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)