On speeding up extended finite state machines using catalyst circuitry

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 583-588

  Huang, Shi Yu ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Automata; Built in self test; Clocks; Combinational circuits; Counting circuits; Logic design; Pipeline processing; Registers; SRAM chips; Timing

Indexed keywords

BUILT-IN SELF TEST; CATALYSTS; CLOCKS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; COUNTING CIRCUITS; DESIGN; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; TIMING CIRCUITS;

AUTOMATA; PIPELINE PROCESSING; REGISTERS; SRAM CHIP; TIMING;

LOGIC CIRCUITS;

EID: 84897851748     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913371     Document Type: Conference Paper

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