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Volumn 2003-January, Issue , 2003, Pages 168-173

Delay testing of MOS transistor with gate oxide short

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; GATES (TRANSISTOR); RECONFIGURABLE HARDWARE;

EID: 84954445098     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250804     Document Type: Conference Paper
Times cited : (18)

References (16)
  • 1
    • 0022313916 scopus 로고
    • Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs
    • C. F. Hawkins and J. M. Soden, "Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs" Int. Test Conference, pp 544-555 1985
    • (1985) Int. Test Conference , pp. 544-555
    • Hawkins, C.F.1    Soden, J.M.2
  • 3
    • 0022875622 scopus 로고
    • Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs
    • C. F. Hawkins and J. M. Soden, "Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs" Int. Test Conference, pp 443-451 1986
    • (1986) Int. Test Conference , pp. 443-451
    • Hawkins, C.F.1    Soden, J.M.2
  • 4
    • 0023595869 scopus 로고
    • Modeling of Spot Defects in MOS Transistors
    • M. Syrzycki, "Modeling of Spot Defects in MOS Transistors" Int. Test Conference, pp 148-157 1987
    • (1987) Int. Test Conference , pp. 148-157
    • Syrzycki, M.1
  • 5
    • 0024627378 scopus 로고
    • Modeling of Gate Oxide Shorts in Mos Transistors
    • March
    • M. Syrzycki, "Modeling of Gate Oxide Shorts in Mos Transistors" Tr. On Computer-Aided Design vol. 8, pp. 193-202, March 1989
    • (1989) Tr. on Computer-Aided Design , vol.8 , pp. 193-202
    • Syrzycki, M.1
  • 6
    • 0025692435 scopus 로고
    • Defect Analysis, Test Generation and Fault Simulation for Gate Oxide Shorts in CMOS ICs
    • S. I. Syed and D.M. Wu, "Defect Analysis, Test Generation and Fault Simulation for Gate Oxide Shorts in CMOS ICs" Int. Symp. Circuits and Syst., pp2705-2707, 1990
    • (1990) Int. Symp. Circuits and Syst. , pp. 2705-2707
    • Syed, S.I.1    Wu, D.M.2
  • 7
    • 0026293032 scopus 로고
    • Analysis and Modeling of MOS Devices with Gate Oxide Short Failures
    • J. Segura, A. Rubio and J. Figueras, "Analysis and Modeling of MOS Devices with Gate Oxide Short Failures" Int. Symp. Circuits and Syst., pp. 2164-2167, 1991
    • (1991) Int. Symp. Circuits and Syst. , pp. 2164-2167
    • Segura, J.1    Rubio, A.2    Figueras, J.3
  • 10
    • 0026954538 scopus 로고
    • Approach to the Analysis of Gate Oxide Shorts in CMOS Digital Circuits
    • J. Segura, J. Figueras and A. Rubio, "Approach to the Analysis of Gate Oxide Shorts in CMOS Digital Circuits" Microeletron. Reliab.,Vol. 32, No 11, pp. 1509-1514, 1992
    • (1992) Microeletron. Reliab. , vol.32 , Issue.11 , pp. 1509-1514
    • Segura, J.1    Figueras, J.2    Rubio, A.3
  • 11
    • 0026970524 scopus 로고
    • Quiescent Current Analysis and Experimentation of Defective CMOS Circuits
    • December
    • J. A. Segura, V. H. Champac, R. Rodriguez-Montanes, J. Figueras and J. A. Rubio, "Quiescent Current Analysis and Experimentation of Defective CMOS Circuits" JETTA No 3, pp.51-62, December 1992
    • (1992) JETTA , Issue.3 , pp. 51-62
    • Segura, J.A.1    Champac, V.H.2    Rodriguez-Montanes, R.3    Figueras, J.4    Rubio, J.A.5
  • 12
    • 0029489006 scopus 로고
    • A Detailed Analysis of GOS Defects in MOS Transistors : Testing Implications at Circuit Level
    • J. Segura, C. De Benito, A. Rubio and C. F. Hawkins, "A Detailed Analysis of GOS Defects in MOS Transistors : Testing Implications at Circuit Level" Int. Test Conference, pp 544-551, 1995
    • (1995) Int. Test Conference , pp. 544-551
    • Segura, J.1    De Benito, C.2    Rubio, A.3    Hawkins, C.F.4
  • 13
    • 0030166437 scopus 로고    scopus 로고
    • A Detailed Analysis and Electrical Modeling of Gate Oxide Shorts in MOS Transistors
    • J. Segura, C. De Benito, A. Rubio and C. F. Hawkins, "A Detailed Analysis and Electrical Modeling of Gate Oxide Shorts in MOS Transistors" JETTA No 8, pp. 229-239, 1996
    • (1996) JETTA , Issue.8 , pp. 229-239
    • Segura, J.1    De Benito, C.2    Rubio, A.3    Hawkins, C.F.4
  • 14
    • 0007735543 scopus 로고    scopus 로고
    • A Complete Analysis of the Voltage Behaviour of MOS Transistor with Gate Oxide Short
    • M. Renovell, J.M. Gallière, F. Azaïs, Y. Bertrand, "A Complete Analysis of the Voltage Behaviour of MOS Transistor with Gate Oxide Short", Defect-Based Testing Work., pp. 5-10, 2001.
    • (2001) Defect-Based Testing Work , pp. 5-10
    • Renovell, M.1    Gallière, J.M.2    Azaïs, F.3    Bertrand, Y.4
  • 16
    • 0035684723 scopus 로고    scopus 로고
    • Boolean and Current Detection of MOS Transistor with Gate Oxide Short
    • M. Renovell, J.M. Gallière, F. Azaïs, Y. Bertrand, "Boolean and Current Detection of MOS Transistor with Gate Oxide Short", Int. Test Conf., pp. 1039-1048, 2001
    • (2001) Int. Test Conf. , pp. 1039-1048
    • Renovell, M.1    Gallière, J.M.2    Azaïs, F.3    Bertrand, Y.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.