Ad hoc grids: Communication and computing in a power constrained environment

IEEE International Performance, Computing and Communications Conference, Proceedings

Volumn , Issue , 2003, Pages 113-122

  Marinescu, Dan C ^a   Marinescu, Gabriela M ^a   Ji, Yongchang ^a   Bölöni, Ladislau ^a   Siegel, Howard Jay ^b  

^a UNIVERSITY OF CENTRAL FLORIDA   (United States)

^b Colorado State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION SYSTEMS; ELECTRIC POWER SUPPLIES TO APPARATUS; EQUIVALENCE CLASSES; FAULT TOLERANT COMPUTER SYSTEMS; MOBILE TELECOMMUNICATION SYSTEMS; NETWORK PROTOCOLS; POWER CONTROL; TELECOMMUNICATION LINKS; DISASTER PREVENTION; DISASTERS; FIREPROOFING; MOBILE DEVICES;

AD HOC GRIDS; MOBILE DEVICES; POWER-CONSTRAINED ENVIRONMENT;

TELECOMMUNICATION EQUIPMENT; ELECTRIC POWER TRANSMISSION NETWORKS;

AD HOC GRID; COMMUNICATION CAPABILITIES; DISASTER MANAGEMENT; HOSTILE ENVIRONMENTS; PEACE-KEEPING OPERATIONS; WILD FIRE;

EID: 84954408244     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. L. Benini, G. de Micheli, "System-level power optimization: Techniques and tools," ACM Transactions on Design Automation and Electronic Systems, Vol. 5, No. 2, pp. 115-192, 2000.
2. K. H. Hodges, "Embedded Micro-component Market Study," DARPA.
3. S. Czerwinski, B. Y. Zhao, T. Hodes, A. D. Joseph, and R. Katz, "An architecture for a secure service discovery service," Proc. of the 5-th Annual ACM/IEEE International Conference on Mobile Computing and Networking (MobiCom-9), ACM Press, pp. 24-35, 1999.
4. J.C. Fabre, and T. Perennou, "A meta-object architecture for fault-tolerant distributed systems," IEEE Transactions on Computers, Vol. 47, No. 1, pp. 78-95, 1998.
5. T. Kidd et al., "An overview of MSHN: The management system for heterogeneous networks," Proc. of the Heterogeneous Computing Workshop (HCW99), IEEE Press, pp. 78-87, 1999.
6. C. T. Hsieh, Q. Wu, C. S. Ding, and M. Pedram, "Statistical sampling and regression analysis for RT-level power evaluation," Proc. of International Conference on Computer Aided Design (ICCAD96), pp. 583-588, 1996.
7. http://menetou.inria.fr/olsr/
8. http://wins.rsc.rockwell.com/WST_Content.html
9. C. X. Huang, B. Zhang, A.-C. Deng, and B. Swirski, "The design and implementation of PowerMill," Proc. of 1995 Symposium on Low Power Design, pp. 105-108, 1995.
10. C. E. Jones, K. M. Sivalingam, P. Agarwal, and J. C. Chen, "A survey of energy efficient protocols for wireless networks," Wireless Networks, Vol. 7, No. 4, pp. 343-358, 2001.
11. M. T.-C. Lee, V. Tiwari, S. Malik, and M. Fujita, "Power analysis and minimization techniques for embedded DSP software," IEEE Transactions on Very Large Scale Integration Systems, Vol. 5, No. 1, pp. 123-135, 1997.
12. H. Mehta, R. M. Owens, M. J. Irvin, R. Chen, and D. Ghosh, "Techniques for low energy software," Proc. of The International Symposium on Low Power Electronics and Design (ISLPED97), pp. 72-75, 1997.
13. F. N. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 1, pp. 310-323, 1993.
14. A. Sinha, and A. P. Chandrakasan, "JouleTrack: A web tool for software energy profiling," Proc. of Design and Automation Conference 2001, pp. 220-225, 2001.
15. A. Savvides, C.-C. Han, and M. B. Strivastava, "Dynamic fine-grained localization in ad-hoc networks of sensors," Proc. of ACM SIGMOBILE 2001, pp. 166-179, 2001.
16. T. Sato, Y. Ootugaro, and H. Tago, "Evaluation of architecture-level power estimation for CMOS-RISC processors," Proc. of The International Symposium on Low Power Electronics and Design (ISLPE95), pp. 44-45, 1995.
17. V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded software: A first step towards power minimization," IEEE Transactions on Very Large Scale Integration Systems, Vol. 2, No. 4, pp. 437-445, 1994.
18. V. Tiwari, S. Malik, A. Wolfe, and M. T.-C. Lee, "Instruction level power analysis and optimization of software," J. VLSI signal Processing Systems, Vol. 13, No. 2/3, pp. 223-238, 1996.
19. http://developer.intel.com/design/pca/applications/index.htm
20. E. Vittoz, "Low power microelectronics: Ways to approach the limits," Proc. of International Conference on Solid-State Circuits 1994, pp. 14-18, 1994.