Solder joint reliability modeling of 96.5Sn/3.5Ag flip chip bumps under temperature cycling condition

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 100-106

  Yeo, A ^a   Lee, C ^a   Pang, J H L ^b  

^a INFINEON TECHNOLOGIES ASIA PACIFIC PTE LTD   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL EFFICIENCY; ELASTOPLASTICITY; ELECTRONICS PACKAGING; FATIGUE OF MATERIALS; FLIP CHIP DEVICES; SCANNING ELECTRON MICROSCOPY; SOLDERED JOINTS;

DEFORMATION BEHAVIOR; FLIP CHIP SOLDER JOINTS; MEAN TIME TO FAILURE; SOLDER JOINT FATIGUE; SOLDER JOINT RELIABILITY; TEMPERATURE CYCLING TESTS; THERMO-MECHANICAL ANALYSIS; VOLUME AVERAGING METHOD;

FINITE ELEMENT METHOD;

EID: 84954064755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271498     Document Type: Conference Paper

References (20)

1. Mulugeta Abtew and Guna Selvaduray, "Lead-free Solders in Microelectronics", Material Science & Engineering, 27 (2000) Pg 95-141
2. Suraski David & Seelig Karl, "The Current Status of Lead-free Solder Alloys", IEEE Transactions on Electronics Packaging Manufacturing, Vol.24, No.4, October 2001
3. Lau J. H. & Lee S.W. R., "Modeling and Analysis of 96.5Sn-3.5Ag Lead-Free Solder Joints of Wafer Level Chip Scale Package on Buildup Microvia Printed Circuit Board", IEEE Transactions on Electronics Packaging Manufacturing, Vol.25, No.1, January 2002
4. Lau, J. H., "Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies", McGraw-Hill, New York, 2000
5. Lau, J. H. and Yi-Hsin Pao, "Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies", McGraw-Hall, New York, 1997
6. Lau, J. H., "Flip Chip Technologies", McGraw-Hill, New York, 1995
7. Pang H. L. J., Chong Y. R. & Low T. H., "Thermal Cycling Analysis of Flip Chip Solder Joint Reliability", IEEE Transactions on Components and Packaging Technologies, December 2001
8. Pang H. L. J. & Chong Y. R., "Modeling Thermal Shock and Cycling Test For Flip Chip Solder Joints", Proceedings of EMTC September 2000, Session 3, Paper 2.
9. Pang H. L. J. & Low T. H., "Thermal Shock & Thermal Cycling Simulations for Flip Chip Solder Joint Reliability Assessment", Proceedings of APACK2001, Singapore
10. th EPTC, Singapore, Dec 2002
11. John H. L. Pang, T. J. Tan, and Y. R. Chong, "Analysis of Underfill Encapsulation Curing Deformations on Flip Chip on Board (FCOB) Package Reliability", Journal of Electronics Manufacturing, Vol.8, Nos. 3 and 4, December 1998
12. "NEMI Lead-free Solder Program - September 2000", http://www.nemi.org/PbFreePUBLIC/index.html
13. "Alloy Selection Tem - January 2001 Press Release", http://www.nemi.org/PbFreePUBLIC/index.html
14. ANSYS User Manual (V7.0), Singapore, 2002
15. Microelectronics Packaging Material Database, Purdue University, Center for Information & Numerical Data Analysis & Synthesis (CINDAS)
16. st ECTC, Las Vegas, Nevada, May 2001
17. th EuroSime, Aix-en Provence, France, April 2003
18. JEDEC Standard, JESD22-A104-B, Temperature Cycling, July 2000
19. Kanchanomai C., Yamamota S., Miyashita Y., Mutoh Y., & A. J. McEvily, "Low Cycle Fatigue Test for Solders Using Non-contact Digital Image Measurement System", International Journal of Fatigue 24 (2002)
20. The American Society for Testings & Materials Standards, ASTM E606: Standard Practice for Strain-controlled Fatigue Testing.