Guidelines for the power constrained design of a CMOS tuned LNA

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2000, Pages 269-272

  Goo, Jung Suk ^a   Oh, Kwang Hoon ^a   Choi, Chang Hoon ^a   Yu, Zhiping ^a   Lee, Thomas H ^a   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGREES OF FREEDOM (MECHANICS); MATHEMATICAL MODELS; MOSFET DEVICES; OPTIMIZATION; THERMAL NOISE;

LOW NOISE AMPLIFIERS (LNA);

AMPLIFIERS (ELECTRONIC);

EID: 0033725017     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)