Reconfigurable shape-adaptive template matching architectures

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 98-110

  Gause, Jörn ^a   Cheung, Peter Y K ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTERS; DESIGN; IMAGE MATCHING; MEMORY ARCHITECTURE; RECONFIGURABLE ARCHITECTURES; VIDEO SIGNAL PROCESSING;

LOGIC RESOURCES; MATCHING PROCESS; RECONFIGURABLE; RECONFIGURABLE COMPUTING; RECONFIGURATION OVERHEAD; RECONFIGURATION TIME; SIZE AND SHAPE; SYSTOLIC ARRAY ARCHITECTURE;

TEMPLATE MATCHING;

EID: 84950162623     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2002.1106665     Document Type: Conference Paper

References (20)

1. MPEG Group, "Overview of the MPEG-4 Standard", ISO/IEC JTC1/SC29/WG11 N4030, March 2001.
2. MPEG Group, "Overview of the MPEG-7 Standard", ISO/IEC JTC1/SC29/WG11 N4031, March 2001.
3. P. Pirsch, C. Reuter, J. P. Wittenburg, M. B. Kulaczewski, H.-J. Stolberg, "Architecture Concepts for Multimedia Signal Processing", Journal of VLSI Signal Processing, vol. 29, no. 3, pp. 157-165, November 2001.
4. L. Torres, M. Kunt, F. Pereira, "Second Generation Video Coding Schemes and Their Role in MPEG-4", European Conf. on Multimedia Applications, Services, and Techniques, May 1996, pp. 799-824.
5. S. D. Haynes, J. Stone, P. Y. K. Cheung, W. Luk, "Video Image Processing with the SONIC Architecture", IEEE Computer, vol. 33, no. 4, pp. 50-57, April 2000.
6. Y. A. Aslandogan, and C. T. Yu, "Techniques and Systems for Image and Video Retrieval", IEEE Trans. Knowledge and Data Engineering, vol. 11, no. 1, pp. 56-63, January/February 1999.
7. T. Komarek, P. Pirsch, "Array Architectures for Block Matching Algorithms", IEEE Trans. on Circuits and Systems, vol. 36, no. 10, October 1989.
8. N. K. Ratha, A. K. Jain, "Computer Vision Algorithms on Reconfigurable Logic Arrays", IEEE Trans. on Parallel and Distributed Systems, vol. 10, no. 1, pp. 29-43, January 1999.
9. J. Villasenor, B. Hutchings, "The Flexibility of Configurable Computing", IEEE Signal Processing Magazine, pp. 67-84, Sept. 1998
10. M. Wirthlin, B. Hutchings, "Improving Functional Density Through Run-Time Reconfiguration", IEEE Trans. on VLSI Systems, vol. 6, no. 2, pp. 247-256, June 1998.
11. M. Wirthlin, B. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", in Proc. FPGA, 1997, pp. 86-92.
12. G. McGregor, and P. Lysaght, "Self Controlling Dynamic Reconfiguration", in Proc. 9th International Workshop on Field-Programmable Logic and Applications, FPL'99, 1999, pp. 144-154.
13. E. Sanchez, M. Sipper, J.-O. Haenni, J.-L. Beuchat, A. Stauffer, and A. Perez-Uribe, "Static and Dynamic Configurable Systems", IEEE Trans. on Computers, vol. 48, no. 6, pp. 556-564, June 1999.
14. P. Lysaght, "Aspects of Dynamically Reconfigurable Logic", in IEE Colloquium on Reconfigurable Systems, Glasgow, Scotland, pp. 1-5, March 1999.
15. J. O. Cadenas, G. M. Megson, and T. P. Plaks "Quantitative Evaluation of Three Reconfiguration Strategies on FPGAs: A Case Study", in HPC-Asia 2000. Proc. of the Fourth Int. Conf. on High-Performance Computing in the Asia-Pacific Region, 2000, pp. 337-342.
16. J. Villasenor, B. Schoner, K.-N. Chia, C. Zapata, H. J. Kim, C. Jones, S. Lansing, B. Mangione-Smith, "Configurable Computing Solutions for Automatic Target Recognition", in Proc. FCCM, pp. 70-79, 1996.
17. J. Gause, P. Y. K. Cheung, W. Luk, "Static and Dynamic Reconfigurable Designs of a 2D Shape-Adaptive DCT", in Proc. FPL, 2000, pp. 96-105.
18. MPEG Group, "MPEG-4 Video Verification Model Version 13.0", ISO/IEC JTC1/SC29/WG11 N2687, March 1999.
19. Xilinx Inc., "Using Shift Register Look-Up Tables", Virtex-II Platform FPGA Handbook, December 2001.
20. Xilinx Inc., "Virtex Series Configuration Architecture User Guide", Application Note XAPP151, September 2000.