Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 7, 1996, Pages 765-774

  Krabbenborg, B H ^a   Bosma, A ^b   De Graaff, H C ^a   Mouthaan, A J ^c  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c GD ANIMAL HEALTH   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CALCULATIONS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE STRUCTURES; TEMPERATURE DISTRIBUTION; THREE DIMENSIONAL;

BIPOLAR JUNCTION TRANSISTOR; ELECTROTHERMAL DEVICE; POWER DISSIPATION;

NETWORKS (CIRCUITS);

EID: 0030190791     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.503944     Document Type: Article

References (12)

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