Optical interconnection as an IP macro of a CMOS library

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn 2001-January, Issue , 2001, Pages 31-35

  Yoshikawa, T ^a   Hatakeyama, I ^a   Miyoshi, K ^a   Kurata, K ^a   Sasaki, J ^a   Kami, N ^a   Sugimoto, T ^a   Fukaishi, M ^a   Nakamura, K ^a   Tanaka, K ^a   Nishi, H ^b   Kudoh, T ^b  

^a NEC CORPORATION   (Japan)

^b Real World Computing Partnership   (Japan)

Author keywords

CMOS logic circuits; High speed optical techniques; Integrated circuit interconnections; Large scale integration; Libraries; Optical attenuators; Optical buffering; Optical design; Optical interconnections; Packaging

Indexed keywords

LIBRARIES; LOGIC CIRCUITS; LOGIC DESIGN; LSI CIRCUITS; OPTICAL COMMUNICATION; OPTICAL DESIGN; OPTICAL INTERCONNECTS; PACKAGING;

CMOS LOGIC CIRCUITS; HIGH SPEED OPTICAL TECHNIQUES; INTEGRATED CIRCUIT INTERCONNECTIONS; OPTICAL ATTENUATORS; OPTICAL BUFFERING;

CMOS INTEGRATED CIRCUITS;

EID: 84950138567     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HIS.2001.946690     Document Type: Conference Paper

References (4)

1. Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, and Michio Yotsuyanagi, "A 20-Gb/s CMOS Murtichannel Transmitter and Receiver Chip Set for Ultra-High-Resolution Digital Displays," IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, Nov. 2000, pp. 1611-1618.
2. special issue "Optical Interconnections for Digital Systems" PROCEEDINGS of the IEEE, No. 6, Vol. 88, June 2000.
3. S. Nishimura, H. Inoue, and T. Yokota, "Optical interconnection subsystem used in the RWC-1 massively parallel computer," IEEE J. Select. Topics Quantum Electron., vol. 5, pp. 360-362, Mar. 1999.
4. T. Yoshikawa, S. Araki, and T. Yokota, "Skewless optical data-link subsystem for massively parallel processors using 8 Gb/s MMF array," IEEE Photon. Technol. Lett., vol. 9, no. 12, pp. 1625-1627, Dec. 1977.