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Volumn 12, Issue 6, 1996, Pages 12-18
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Coupling effects on wire delay
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Author keywords
[No Author keywords available]
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Indexed keywords
CAPACITANCE;
CMOS INTEGRATED CIRCUITS;
COMPUTER AIDED DESIGN;
COMPUTER SIMULATION;
COMPUTER SOFTWARE;
ELECTRIC DELAY LINES;
ELECTRIC FIELD EFFECTS;
ELECTRIC NETWORK PARAMETERS;
INTEGRATED CIRCUIT LAYOUT;
RANDOM ACCESS STORAGE;
ELECTRIC SIGNAL PROPAGATION DELAY;
WIRE COUPLING EFFECTS;
VLSI CIRCUITS;
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EID: 0030285556
PISSN: 87553996
EISSN: None
Source Type: Journal
DOI: 10.1109/101.544446 Document Type: Article |
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Times cited : (9)
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References (0)
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