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Volumn 2000-January, Issue , 2000, Pages 291-298

A layout approach for electrical and physical design integration of high-performance analog circuits

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG CIRCUITS;

EID: 84950127067     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838885     Document Type: Conference Paper
Times cited : (20)

References (12)
  • 2
    • 0025383839 scopus 로고
    • OPASYN: A compiler for CMOS operational amplifiers
    • Feb.
    • H. Y. Koh, C. H. Sequin, and P. R. Gray. "OPASYN: A Compiler for CMOS Operational Amplifiers, ". IEEE Trans. Computer-Aided Design, Feb. 1990, 9(2):113-125.
    • (1990) IEEE Trans. Computer-aided Design , vol.9 , Issue.2 , pp. 113-125
    • Koh, H.Y.1    Sequin, C.H.2    Gray, P.R.3
  • 4
    • 0026118974 scopus 로고
    • KOAN/ANAGRAM II: New tools for device-level analog placement and routing
    • Mar.
    • J. M. Cohn, R. A. Rutenbar, and L. R. Carley. "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing, ". IEEE J. of Solid-State Circuits, Mar. 1991, 26(3):330-342.
    • (1991) IEEE J. of Solid-state Circuits , vol.26 , Issue.3 , pp. 330-342
    • Cohn, J.M.1    Rutenbar, R.A.2    Carley, L.R.3
  • 6
    • 0029345604 scopus 로고
    • A performance-driven placement tool for analog integrated circuits
    • July
    • K. Lampaert, G. Gielen, and W. M. Sansen. "A Performance-Driven Placement Tool for Analog Integrated Circuits, ". IEEE J. of Solid-State Circuits, July 1995, 30(7):773-780.
    • (1995) IEEE J. of Solid-state Circuits , vol.30 , Issue.7 , pp. 773-780
    • Lampaert, K.1    Gielen, G.2    Sansen, W.M.3
  • 7
    • 0025414530 scopus 로고
    • Operational-amplifier compilation with performance optimization
    • Apr.
    • H. Onodera, H. Kanbara, and K. Tamaru. "Operational-Amplifier Compilation with Performance Optimization, ". IEEE J. of Solid-State Circuits, Apr. 1990, 25(2):466-473.
    • (1990) IEEE J. of Solid-state Circuits , vol.25 , Issue.2 , pp. 466-473
    • Onodera, H.1    Kanbara, H.2    Tamaru, K.3
  • 8
  • 10
    • 0029220994 scopus 로고
    • Optimum CMOS stack generation with analog constraints
    • Jan.
    • E. Malavasi and D. Pandini. "Optimum CMOS Stack Generation with Analog Constraints, ". IEEE Trans. Computer-Aided Design, Jan. 1995, 14(1):107-122.
    • (1995) IEEE Trans. Computer-aided Design , vol.14 , Issue.1 , pp. 107-122
    • Malavasi, E.1    Pandini, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.