Cache memory design for network processors

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 409-418

  Chiueh, Tzi Cker ^a   Pradhan, Prashant ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INTERNET; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PACKET SWITCHING; ROUTERS; TELECOMMUNICATION TRAFFIC;

CENTRAL PROCESSING UNIT; NETWORK PACKET PROCESSING; NETWORK PROCESSOR; ROUTING;

BUFFER STORAGE;

EID: 0033325732     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)