A 20k-spin Ising chip to solve combinatorial optimization problems with CMOS annealing

IEEE Journal of Solid-State Circuits

Volumn 51, Issue 1, 2016, Pages 303-309

  Yamaoka, Masanao ^a   Yoshimura, Chihiro ^a   Hayashi, Masato ^a   Okuyama, Takuya ^a   Aoki, Hidetaka ^a   Mizuno, Hiroyuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

CMOS annealing; Combinatorial optimization problem; Ising computing; Ising model; Natural computing; SRAM; Variation

Indexed keywords

APPROXIMATION ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL OPTIMIZATION; COMPUTER ARCHITECTURE; ISING MODEL; OPTIMIZATION;

CMOS CIRCUITS; COMBINATORIAL OPTIMIZATION PROBLEMS; COMPUTING ARCHITECTURE; CONVERGENCE PROPERTIES; MAGNETIC SPIN; POWER EFFICIENCY;

PROBLEM SOLVING;

EID: 84949920941     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2015.2498601     Document Type: Article

References (11)

1. F. Barahona, M. Grötschel, M. Jünger, and G. Reinelt, "An application of combinatorial optimization to statistical physics and circuit layout design," Oper. Res., vol. 36, pp. 493-513, 1988.
2. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA, USA: Freeman, 1979.
3. F. Barahona, "On the computational complexity of Ising spin glass models," J. Phys. A Math. Gen., vol. 15, pp. 3241-3253, 1982.
4. A. Lucas, "Ising formulations of many NP problems," Front. Phys., Feb. 2014, doi:10.3389/fphy.2014.00005.
5. W. Johnson et al., "Quantum annealing with manufactured spins," Nature, vol. 473, pp. 194-198, May 2011.
6. R. F. Service, "The brain chip," Science, vol. 345, no. 6197, pp. 614-616, Aug. 2014.
7. C. Yoshimura et al., "Spatial computing architecture using randomness of memory cell stability under voltage control," in Proc. 21st Eur. Conf. Circuit Theory Des. (ECCTD'13), Sep. 2013.
8. M. Yamaoka et al., "20k-spin Ising chip for combinational optimization problem with CMOS annealing," in IEEE Int. Solid-State Circuits Conf. (ISSCC'15) Dig. Tech. Papers, Feb. 2015, pp. 432-433.
9. M. J. Pelgrom and A. C. J. Duinmaijar, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
10. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
11. S. Kahruman et al., "On greedy construction heuristics for the max-cut problem," Int. J. Comput. Sci. Eng., vol. 3, no. 3, pp. 211-218, 2007.