20k-spin Ising chip for combinational optimization problem with CMOS annealing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 432-433

  Yamaoka, Masanao ^a   Yoshimura, Chihiro ^a   Hayashi, Masato ^a   Okuyama, Takuya ^a   Aoki, Hidetaka ^a   Mizuno, Hiroyuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG COMPUTERS; ANNEALING; CMOS INTEGRATED CIRCUITS; GROUND STATE; ISING MODEL;

COMBINATIONAL OPTIMIZATION; COMPUTING PARADIGM; CONVERGENCE PROPERTIES; INTERACTION COEFFICIENT; NEUMANN ARCHITECTURE; SEMICONDUCTOR SCALING; SEQUENTIAL COMPUTING; STATE TRANSITIONS;

COMPUTER ARCHITECTURE;

EID: 84940726933     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7063111     Document Type: Conference Paper

References (3)

1. M. W. Johnson, et al., "Quantum annealing with manufactured spins, " Nature, Vol. 473, pp. 194-198, May 12, 2011.
2. R. F. Service, "The brain chip, " Science, Vol. 345, no. 6197, pp. 614-616, Aug. 8, 2014.
3. C. Yoshimura, et al., "Spatial computing architecture using randomness of memory cell stability under voltage control", 21st European Conference on Circuit Theory and Design, Sept. 2013.