Spatial computing architecture using randomness of memory cell stability under voltage control

2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings

Volumn , Issue , 2013, Pages

  Yoshimura, Chihiro ^a   Yamaoka, Masanao ^a   Aoki, Hidetaka ^a   Mizuno, Hiroyuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CIRCUIT THEORY; COMPUTATION THEORY; CYTOLOGY; GROUND STATE; ISING MODEL; RANDOM PROCESSES; SEMICONDUCTOR STORAGE; TRAVELING SALESMAN PROBLEM;

COMPUTER PERFORMANCE; COMPUTING ARCHITECTURE; MEMORY CELL ARRAYS; PRACTICAL PROBLEMS; PROBABILISTIC BEHAVIOR; PROPOSED ARCHITECTURES; SOFTWARE AND HARDWARES; SPATIAL PARAMETERS;

MEMORY ARCHITECTURE;

EID: 84892639473     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ecctd.2013.6662276     Document Type: Conference Paper

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