Analysis of erratic bits in flash memories

IEEE International Reliability Physics Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 17-22

  Chimenton, A ^a   Pellati, P ^a   Olivo, P ^a  

^a UNIVERSITY OF FERRARA   (Italy)

Author keywords

Circuits; Conductivity; Contamination; Dielectric devices; Flash memory; Nonvolatile memory; Shape control; Testing; Threshold voltage; Tunneling

Indexed keywords

CONTAMINATION; DIELECTRIC DEVICES; ELECTRIC CONDUCTIVITY; ELECTRON TUNNELING; ELECTRONIC EQUIPMENT TESTING; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); TESTING; THRESHOLD VOLTAGE;

BARRIER HEIGHTS; ERASE OPERATION; FOWLER-NORDHEIM INJECTION; LINEAR RELATIONSHIPS; NON-VOLATILE MEMORY; PHYSICAL NATURE; SHAPE CONTROL; THRESHOLD SHIFTS;

FLASH MEMORY;

EID: 84949798605     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2001.922875     Document Type: Conference Paper

References (8)

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8. A. Kolodny, S. T. K. Nieh, B. Eitan, and J. Shappir, "Analysis and Modeling of Floating-Gate EEPROM Cells," IEEE Transaction on Electron Devices, vol. 33, pp. 835-844, June 1986.