The use of historical defect imagery for yield learning

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn 2000-January, Issue , 2000, Pages 18-25

  Tobin, K W ^a   Karnowski, T P ^a   Lakhani, F ^b  

^a OAK RIDGE NATIONAL LABORATORY   (United States)

^b Yield Management Tools Program   (United States)

Author keywords

Acceleration; Complexity theory; Fabrication; Failure analysis; Information retrieval; Integrated circuit technology; Integrated circuit yield; Laboratories; Manufacturing processes; Monitoring

Indexed keywords

ACCELERATION; DEFECTS; ELECTRIC NETWORK ANALYSIS; FABRICATION; FAILURE ANALYSIS; INFORMATION RETRIEVAL; INTEGRATED CIRCUITS; LABORATORIES; MANUFACTURE; MONITORING; QUERY PROCESSING; SCREENING; SEMICONDUCTOR DEVICE MANUFACTURE;

COMPLEXITY THEORY; INTEGRATED CIRCUIT FABRICATION; INTEGRATED CIRCUIT TECHNOLOGY; INTERNATIONAL SEMATECH; LARGE IMAGE DATABASE; MANUFACTURING PROCESS; OAK RIDGE NATIONAL LABORATORIES; RAPID IDENTIFICATION;

IMAGE PROCESSING;

EID: 84949762443     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2000.902553     Document Type: Conference Paper

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