A novel methodology for hierarchical test generation using functional constraint composition

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 9-14

  Vedula, V M ^a   Abraham, J A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Automatic test pattern generation; Design engineering; Hardware design languages; Jacobian matrices; Logic; Manufacturing; Process design; Test pattern generators; Testing; Transistors

Indexed keywords

ARM PROCESSORS; BENCHMARKING; DESIGN; EXTRACTION; JACOBIAN MATRICES; MANUFACTURE; PROCESS DESIGN; TESTING; TRANSISTORS;

CONSTRAINT EXTRACTION; DESIGN ENGINEERING; FUNCTIONAL CONSTRAINTS; HARDWARE DESIGN LANGUAGE; LOGIC; MANUFACTURING TESTS; MODULE UNDER TESTS; TEST PATTERN GENERATOR;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84949667652     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889552     Document Type: Conference Paper

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