Hardware/software co-debugging for reconfigurable computing

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 59-63

  Tomko, K A ^a   Tiwari, A ^a  

^a University of Cincinnati   (United States)

Author keywords

Application software; Circuit faults; Circuit simulation; Clocks; Coprocessors; Field programmable gate arrays; Graphical user interfaces; Hardware; Software debugging; Software performance

Indexed keywords

APPLICATION PROGRAMS; CIRCUIT SIMULATION; CLOCKS; COMPUTER DEBUGGING; COMPUTER HARDWARE; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GRAPHICAL USER INTERFACES; HARDWARE; MICROPROCESSOR CHIPS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SOFTWARE TESTING; USER INTERFACES;

APPLICATION DEVELOPMENT ENVIRONMENT; CIRCUIT FAULTS; CO-PROCESSORS; RECONFIGURABLE COMPUTING; RESEARCH AND DEVELOPMENT PROJECTS; SOFTWARE AND HARDWARES; SOFTWARE DEBUGGING; SOFTWARE PERFORMANCE;

PROGRAM DEBUGGING;

EID: 84949655785     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889560     Document Type: Conference Paper

References (13)

1. ChipScope ILA™ home page. http://www.xilinx.com/products/software/chipscope/index.htm.
2. W. J. Fang, A. C.-H. Wu, and T. Y. Yen. A real-time rtl engineering change method supporting on-line debugging for logic-emulation applications. In Proceeding of 34th Design Automation Conference, pages 101-106, June 1997. Anheim.
3. P. Graham, B. L. Hutchings, and B. Nelson. Improving the FPGA design process through determining and applying logicl-to-physical design mappings. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines., April 2000.
4. S. Hanono. Innerview hardware debugger: A logic analysis tool for the virtual wires emulation system. Master's thesis, Massachusetts Institute of Technology, February 1995.
5. B. L. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD suite for high performance FPGA design. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines., pages 12-23, April 1999.
6. B. L. Hutchings and B. E. Nelson. Using general-purpose programming languages for fpga design. In Proceeding of 37th Design Automation Conference, pages 561-566, June 2000. Los Angeles.
7. R. Klein and R. Nelson. Seamles CVE™: Hardware/software co-verification technology. Technical publication, Mentor Graphics Corportation. http://www.mentor.com/seamless/.
8. Model technology's modelsim home page. http://www.model.com/.
9. Quickturn home page. http://www.quickturn.com/.
10. J. A. Rowson. Hardware/software co-simulation. In Proceeding of 33th Design Automation Conference, 1996.
11. Wildforce users manual.
12. Using xilinx and synplify for incremental designing (eco). Technical Report XAP164, Xilinx, August 1999.
13. J. S. Yim, Y. H. Hwang, C. J. Park, H. Choi, W. S. Yang, H. S. Oh, I. C. Park, and C. M. Kyung. A c-based rtl design verification methodology for complex microprocessor. In Proceeding of 34th Design Automation Conference, pages 83-88, June 1997. Anheim.