Improving the FPGA design process through determining and applying logical-to-physical design mappings

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 305-306

  Graham, Paul ^a   Hutchings, Brad ^a   Nelson, Brent ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER DEBUGGING; COMPUTERS; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; MAPPING;

DESIGN ELEMENTS; DESIGN ENVIRONMENT; FPGA DESIGN; LOGICAL DESIGN; PARTIAL MAPPINGS; PHYSICAL DESIGN; PLATFORM INDEPENDENT;

INTEGRATED CIRCUIT DESIGN;

EID: 84949792121     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903429     Document Type: Conference Paper

References (5)

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2. B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A cad suite for highperformance fpga design", in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines (K. L. Pocek and J. M. Arnold, eds.), (Napa, CA), p. n/a, IEEE Computer Society, IEEE, April 1999.
3. W. Hölfich, "Using the XC4000 readback capability", Application Note XAPP 015, Xilinx, XC4000, San Jose, CA, 1994.
4. C. Carmichael, "VIRTEX configuration and readback", Application Note XAPP 138, Xilinx, San Jose, CA, March 1999.
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