90% write power saving SRAM using sense-amplifying memory cell

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 46-47

  Hattori, Sadaaki ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; VOLTAGE CONTROL;

SENSE AMPLIFYING MEMORY CELL; WRITE POWER SAVING MEMORY;

STATIC RANDOM ACCESS STORAGE;

EID: 0242443409     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, and Shin Mitarai, "Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques", IEEE J. Solid-State Circuits, vol.33, No.11, pp.1659-1671, Nov., 1998