A sub-0.5 v dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies

Proceedings of the International Conference on Microelectronics, ICM

Volumn 2001-January, Issue , 2001, Pages 75-78

  Elgebaly, Mohamed ^a   Sachdev, Manoj ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; MICROELECTRONICS;

BULK CMOS; CARRY SKIP ADDERS; DYNAMIC THRESHOLD; ENERGY APPLICATIONS; LOW VOLTAGES; PMOS TRANSISTORS; SWITCHING SPEED;

CMOS INTEGRATED CIRCUITS;

EID: 84949236418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2001.997491     Document Type: Conference Paper

References (7)

1. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. Ko, and C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI", IEEE Transactions on Electron Devices, vol. 44, no. 3, pp. 414-421, March 1997.
2. J. Rabaey, Digital Integrated Circuits: A Design Perspective., Upper Saddle River, Prentice Hall, N. J., 1996.
3. R. Zimmermann and W. Fichtner, "Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic", IEEE Journal of Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.
4. W. Jin, P. Chan, Andjvl Chan, "On the Power Dissipation in Dynamic Threshold Silicon-On-Insulator CMOS Inverter", IEEE Transactions on Electron Devices, vol. 45, no. 8, pp. 1717-1724, Augest 1998.
5. H. Kawaguchi, K. Nose, and T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current", IEEE Journal of Solid State Circuits, vol. 35, no. 10, pp. 1498-1501, October 2000.
6. I. S. Abu-Khater, A. Bellaouar, M. I. Elmasry, and R. H. Yan, "Circuit/architecture for low-power high-performance 32-bit adder", in Proceedings of the Fifth Great Lakes Symposium on VLSI, 1995, pp. 74-77.
7. V. Kantabutra, "Designing optimum carry-skip adders", in Proceedings of the 10th Symposium on Computer Arithmetic, 1991, pp. 146-153.