Mechanizing verification of arithmetic circuits: SRT division

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1346, Issue , 1997, Pages 103-122

  Kapur, Deepak ^a   Subramaniam, M ^b  

^a State University of New York   (United States)

^b HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; DECISION THEORY; DIGITAL ARITHMETIC; NUMBER THEORY; SOFTWARE ENGINEERING; TIMING CIRCUITS;

ARITHMETIC CIRCUIT; DECISION PROCEDURE; DIVIDER CIRCUITS; DIVISION CIRCUIT; EQUATIONAL SPECIFICATIONS; PENTIUM PROCESSORS; PRESBURGER ARITHMETIC; THEOREM PROVERS;

LOGIC CIRCUITS;

EID: 84949219848     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0058026     Document Type: Conference Paper

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