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Volumn 1102, Issue , 1996, Pages 135-146

Mechanically verifying a family of multiplier circuits

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER HARDWARE; HARDWARE; SPECIFICATIONS;

EID: 84957366809     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61474-5_64     Document Type: Conference Paper
Times cited : (17)

References (20)
  • 3
    • 0022769976 scopus 로고
    • Graph-based Algorithms for boolean function manipulation
    • Bryant R.E., "Graph-based Algorithms for boolean function manipulation", IEEE trans, on Computers, C-35(8), 1986.
    • (1986) IEEE Trans, on Computers, C-35 , Issue.8
    • Bryant, R.E.1
  • 7
    • 0001342967 scopus 로고
    • Some Schemes for parallel multipliers
    • Swartzlander Jr. (editor), IEEE Computer Society Press
    • L. Dadda "Some Schemes for parallel multipliers," in Computer Arithmetic Vol. l, E.E. Swartzlander Jr. (editor), IEEE Computer Society Press, 1990.
    • (1990) Computer Arithmetic , vol.1
    • Dadda, L.1
  • 9
    • 0025211732 scopus 로고
    • Design of the IBM RISC System/6000 floating-point execution unit
    • R.K. Montoye, E. Hokenek and S.L. Runyon, "Design of the IBM RISC System/6000 floating-point execution unit," IBM Journal, Vol. 34, No. 1, 1990.
    • (1990) IBM Journal , vol.34 , Issue.1
    • Montoye, R.K.1    Hokenek, E.2    Runyon, S.L.3
  • 10
    • 84957390048 scopus 로고
    • "Theorem Provers in circuit design', IFIP Transactions, V. Stavridou, T.F. Melham, R.T. Boute (eds.) N.Holland
    • "Theorem Provers in circuit design', IFIP Transactions, V. Stavridou, T.F. Melham, R.T. Boute (eds.) N.Holland 1992.
    • (1992)
  • 14
    • 84893812416 scopus 로고
    • VHDL Description and Formal Verification of Systolic Multipliers
    • D. Agnew and L. Claesen (eds.) N. Holland
    • L. Pierre, "VHDL Description and Formal Verification of Systolic Multipliers," in Proc. of CHDL, D. Agnew and L. Claesen (eds.) N. Holland 1993.
    • (1993) Proc. Of CHDL
    • Pierre, L.1
  • 17
    • 0025493701 scopus 로고
    • Formal Verification of a pipelined microprocessor
    • Sept
    • M. Srivas and M. Bickford, "Formal Verification of a pipelined microprocessor.", IEEE Software, Sept. 1990.
    • (1990) IEEE Software
    • Srivas, M.1    Bickford, M.2
  • 18
    • 0345270806 scopus 로고
    • Verified Functions for Generating Signed-Binary Arithmetic Hardware
    • Dec
    • Shui-Kai Chin, "Verified Functions for Generating Signed-Binary Arithmetic Hardware", 1EEE trans, on Computer Aided Design, Vol. 1t, No. 12, Dec. 1992.
    • (1992) 1EEE Trans, on Computer Aided Design , vol.1 , Issue.12
    • Chin, S.-K.1
  • 19
    • 84957390052 scopus 로고    scopus 로고
    • Correctness Proofs of Parameterized Hardware Modules in the Cathedral-II Synthesis Environment
    • Glasgow, Scotland
    • D. Verkest, L. Claesen, and H. De Man, "Correctness Proofs of Parameterized Hardware Modules in the Cathedral-II Synthesis Environment", EDA C'90, Glasgow, Scotland, March 1999.
    • (1999) EDA C'90
    • Verkest, D.1    Claesen, L.2    De Man, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.