Modeling, extraction and simulation of CMOS I/O circuits under ESD stress

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1998, Pages 389-392

  Li, Tong ^a   Tsai, Ching Han ^a   Rosenbaum, Elyse ^a   Kang, Sung Mo ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTRIC RESISTANCE; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SUBSTRATES; VLSI CIRCUITS;

INPUT/OUTPUT CIRCUITS; SUBSTRATE-COUPLING EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 0031622881     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)