Formalization and proof of a solution to the PCI 2.1 bus transaction ordering problem

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1522, Issue , 1998, Pages 237-254

  Mokkedem, Abdel ^a   Hosabettu, Ravi ^a   Gopalakrishnan, Ganesh ^a  

^a UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL METHODS;

CORRECTNESS PROPERTIES; ORDER PROBLEMS; STANDARD BUS;

COMPUTER AIDED DESIGN;

EID: 84948976491     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49519-3_17     Document Type: Conference Paper

References (14)

1. Ricky W. Butler and Jon A. Sjogren. A PVS Graph Theory Library. Technical Report Memorandum, NASA Langly Research Center, December 1997. http://atb-www.larc.nasa.gov/ftp/larc/PVS-library.
2. E. M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D. E. Long, K. L. McMillan, and L. A. Ness. Verification of the futurebus+ cache coherence protocol. In L. Claesen, editor, Eleventh International Symposium on Computer Hardware Description Languages and their Applications. North-Holland, April 1993.
3. Francisco Corella. Verifying memory ordering model of I/O systems. In Invited talk at Computer Hardware Description Languages 1997, Toledo, Spain, April 1997.
4. Francisco Corella, Robert Shaw, and Cui Zhang. A formal proof of absence of deadlock for any acyclic network of PCI buses. In Computer Hardware Description Languages, 1997.
5. Rajnish Ghughal, Abdel Mokkedem, Ratan Nalumasu, and Ganesh Gopalakrishnan. Using “test model-checking” to verify the runway-pa8000 memory model. In Tenth Annual ACM Symposium On Parallel Algorithms And Architectures, pages 231-239, Puerto Vallarta, Mexico, June 1998. ACM Press.
6. G. Gopalakrishnan, R. Ghughal, R. Hosabettu, A. Mokkedem, and R. Nalumasu. Formal modeling and validation applied to a commercial coherent bus: A case study. In Hon F. Li and David K. Probst, editors, CHARME, Montreal, Canada, 1997.
7. PCI Special Interest Group. PCI Local Bus Specification, Revision 2.1, June 1995.
8. A. Mokkedem. Verification of PCI 2.1 Local Bus in PVS. http://www.cs.utah.edu/~mokkedem/pvs/pvs.html.
9. Vijay Nagasamy, Sreeranga Rajan, and Preeti R. Panda. Fiber channel protocol: Formal specification and verification. In Sixth Annual Silicon Valley Networking Conference, 1997.
10. Ratan Nalumasu, Rajnish Ghughal, Abdel Mokkdem, and Ganesh Gopalakrishnan. The ‘test model-checking’ approach to the verification of formal memory models of multiprocessors. In Alan J. Hu and Moshe Y. Vardi, editors, Computer Aided Verification, volume 1427 of LNCS, pages 464-476, Vancouver, BC, Canada, June 1998. Springer-Verlag.
11. Sam Owre, John Rushby, Natarajan Shankar, and Friedrich von Henke. Formal verification for fault-tolerant architectures: Prolegomena to the design of PVS. IEEE Transactions on Software Engineering, 21(2):107-125, February 1995.
12. F. Corella. Hewlett Packard. Proposal to fix ordering problem in PCI 2.1, 1996. http://www.pcisig.com/reflector/thrd8.html\#00706.
13. S. Park and D. L. Dill. Protocol verification by aggregation of distributed trans- actions. In Rajeev Alur and Thomas A. Henzinger, editors, Computer Aided Verification, volume 1102 of Lecture Notes in Computer Science, pages 300-309, New Brunswick, NJ, USA, July 1996. Springer-Verlag.
14. Edward Solari and George Willse. PCI Hardwarde and Software Architecture & Design. Annabooks, 3rd edition edition, December 1996. ISBN 0-929392-32-9.