Linear array processors with multiple access modes memory for real-time image processing

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 1, Issue , 2002, Pages 203-206

  Rabah, H ^a   Mathias, H ^a   Mozef, E ^b   Torres, D ^c   Weber, S ^a  

^a INSTITUT JEAN LAMOUR   (France)

^b BANDUNG INSTITUTE OF TECHNOLOGY   (Indonesia)

^c INSTITUTO TECNOLÓGICO DE MORELIA   (Mexico)

Author keywords

CADCAM; Communication networks; Computer aided manufacturing; Image processing; MONOS devices; Parallel architectures; Random access memory; Read write memory; Real time systems; VLIW

Indexed keywords

ARRAY PROCESSING; ASSOCIATIVE STORAGE; CAMS; COMPUTER AIDED MANUFACTURING; COMPUTER ARCHITECTURE; IMAGE COMMUNICATION SYSTEMS; INTERACTIVE COMPUTER SYSTEMS; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; TELECOMMUNICATION NETWORKS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

CADCAM; HARDWARE SIMULATION; INTERMEDIATE LEVEL; LABELING ALGORITHMS; MONOS DEVICES; RANDOM ACCESS MEMORY; REAL-TIME IMAGE PROCESSING; VLIW;

IMAGE PROCESSING;

EID: 84948945898     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2002.1114937     Document Type: Conference Paper

References (8)

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