Efficient reduction of susceptance-based package models using PRIMA

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn 2002-January, Issue , 2002, Pages 33-36

  Celik, Mustafa ^a   Zheng, Hui ^b   Pileggi, Lawrence ^b  

^a Monterey Design Systems   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA PRIVACY; ELECTRONICS PACKAGING; INVERSE PROBLEMS; MATRIX ALGEBRA; NETWORK SECURITY;

INDUCTANCE MATRIX; INTERCONNECT CIRCUITS; PACKAGE MODELS; REDUCED ORDER MODELS;

MAGNETIC COUPLINGS;

EID: 84948779356     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2002.1057877     Document Type: Conference Paper

References (10)

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2. M. Celik, L. Pileggi, and A. Odabasioglu, ICInterronnect Analysis, Kluwer Academic Publishers, 2002.
3. A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: Introducing a new circuit element K," Proc. ICCQD, Nov. 2000.
4. M. Beattie and L. Pileggi, "Efficient inductance extraction via windowing," Proc. of DATE, Mar. 2001.
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6. T. Chen an C. Chen, "Eficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods," in Proc. 38th DAC, June 2001.
7. H. Zheng, et. al., "Window-based susceptance models for large-scale RLC circuit analyses," Proc. 2002 DATE, March 2002.
8. H. Zheng, et. al. "Robust and passive model order reduction for circuits containing susceptance elemenents," to appear in ICCAD 2002
9. A. George and J. Liu, Computer Solution of Large Sparse Positive Defnite Systems, Prentice-Hall Inc., 1981.
10. Muttab User 5 Guide, The Math Works, Inc., Natick, MA, 2000.