Architecture and hardware for scheduling gigabit packet streams

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn 2002-January, Issue , 2002, Pages 52-61

  Krishnamurthy, Raj ^a   Yalamanchill, Sudhakar ^a   Schwan, Karsten ^a   West, Richard ^b  

^a Georgia Institute of Technology   (United States)

^b BOSTON UNIVERSITY   (United States)

Author keywords

Computer architecture; Computer networks; Ethernet networks; Field programmable gate arrays; Hardware; Network servers; Processor scheduling; Streaming media; Switches; Web server

Indexed keywords

CLUSTER COMPUTING; COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER NETWORKS; COMPUTER PERIPHERAL EQUIPMENT; ETHERNET; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT INTERCONNECTS; INTEROPERABILITY; MEDIA STREAMING; NETWORK ARCHITECTURE; SCHEDULING; SERVERS; SWITCHES;

ETHERNET NETWORKS; NETWORK SERVER; PROCESSOR SCHEDULING; STREAMING MEDIA; WEB SERVERS;

COMPUTER HARDWARE;

EID: 84948757305     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CONECT.2002.1039257     Document Type: Conference Paper

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