Hardware-efficient fair queueing architectures for high-speed networks

Proceedings - IEEE INFOCOM

Volumn 2, Issue , 1996, Pages 638-646

  Rexford, Jennifer L ^a   Greenberg, Albert G ^a   Bonomi, Flavio G ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); HIERARCHICAL SYSTEMS; PACKET SWITCHING; PERFORMANCE; QUEUEING THEORY; TELECOMMUNICATION LINKS; TELECOMMUNICATION TRAFFIC;

HARDWARE EFFICIENT FAIR QUEUEING ARCHITECTURE; HIGH SPEED NETWORKS; SELF CLOCKED FAIR QUEUEING;

BROADBAND NETWORKS;

EID: 0029778714     PISSN: 0743166X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)