The effects of STI process parameters on the integrity of dual gate oxides

IEEE International Reliability Physics Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 48-51

  Lim, Hoon ^a   Lee, Seung Jae ^a   Youn, Jong Mil ^a   Ha, Tae Hong ^a   Kim, Jin Ho ^a   Choi, Bong Hyun ^a   Kim, Ki Joon ^a   Kim, Ho Jin ^a   Kim, Kyeong Tae ^a   Byun, Hyun Geun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Breakdown voltage; Design for quality; Fabrication; Filling; Oxidation; Planarization; Random access memory; Stress; Temperature; Wet etching

Indexed keywords

ELECTRIC BREAKDOWN; FABRICATION; FILLING; GATES (TRANSISTOR); MOS DEVICES; OXIDATION; RANDOM ACCESS STORAGE; RELIABILITY; STRESSES; TEMPERATURE; WET ETCHING;

DESIGN FOR QUALITIES; FABRICATION PROCESS; INFERIOR QUALITY; PLANARIZATION; PROCESS PARAMETERS; RANDOM ACCESS MEMORY; SHALLOW-TRENCH-ISOLATION PROCESS; TRENCH FILLINGS;

SEMICONDUCTING SILICON;

EID: 84948662867     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2001.922880     Document Type: Conference Paper

References (6)

1. Y. Goto et al., "A Triple Gate Oxide CMOS Technology Using Fluorine Implant for System-on-a-Chip." in Proceedings of the Symp. On VLSI Tech., 2000, pp. 148-149.
2. N. Bhat et al., "Hot Carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25um CMOS technology for embedded applications," in Proceeding of International Electron Devices Meeting, 1998, pp.931-934.
3. H. Lim, "Reverse Short Channel Effects in Shallow Trench Isolated MOSFET," in Proceedings of the Conference on Solid State Devices and Materials, 2000, pp. 170-171.
4. S.-W. Lee et. al., "Gate Oxide Thinning Effects at the Edge of Shallow Trench Isolation in the Dual Gate Oxide Process," in Proceedings of the Conference on VLSI and CAD, 1999, pp. 249-252.
5. M. Nandakumar et al., "Shallow Trench Isolation for advanced ULSI CMOS Technologies," IEDM Tech. Digest, 1998, pp. 133-136.
6. C.T. Liu et al., "Severe Thickness Variation of Sub-3nm Gate Oxide Due to Si Surface Faceting, Poly-Si Intrusion and Corner Stress," in Proceedings of the Symp. On VLSI Tech., 1999, pp. 75-76.